1. Field of the Invention
The present invention generally relates to a CMOS output buffer unit, and more specifically, to a technology of providing a predetermined output current regardless of change of a power voltage, thereby stabilizing power.
2. Description of the Prior Art
Generally, a Complementary Metal Oxide Semiconductor (hereinafter, referred to as “CMOS”) output buffer circuit comprises a plurality of CMOS transistors connected in parallel each including a P-channel Metal Oxide Semiconductor (hereinafter, referred to as “PMOS”) Transistor and a N-channel Metal Oxide Semiconductor (hereinafter, referred to as “NMOS”) Transistor.
FIG. 1 is a circuit diagram of a conventional CMOS output buffer circuit.
The conventional CMOS output buffer circuit comprises an inverter IN1, a NAND gate NAND1, a buffer BUF1, a PMOS transistor PM1 and a NMOS transistor NM1.
The NAND gate NAND1 outputs a high level signal regardless of a level of a data signal DATA if a stop signal STOP is at a high level. The buffer BUF1 buffers the high level signal outputted from the NAND gate NAND1, and the NMOS transistor NM1 driven by an output signal from the buffer BUF1 outputs an output signal OUT having a low level.
Meanwhile, the CMOS output buffer circuit outputs the output signal OUT in response to the data signal DATA if the stop signal STOP is at a low level. If the data signal DATA is at a high level, the PMOS transistor PM1 is driven and the CMOS output buffer circuit outputs the output signal OUT having a high level. If the data signal DATA is at a low level, the NMOS transistor NM1 is driven and the CMOS output buffer circuit outputs the output signal OUT at a low level.
In the above-described conventional CMOS output buffer circuit, if a power voltage VDD increases, current flowing through the PMOS transistor PM1 dramatically increases. As a result, the output current becomes temporarily unstable depending on toggling of the data signal DATA.
FIG. 2 is a timing diagram of a conventional CMOS output buffer circuit.
As shown in FIG. 2, in an interval where the stop signal STOP is at a low level and the data signal DATA is normally outputted, the change (ranging from 22 mA to 66 mA) of the current driving ability of output signal OUT from the CMOS output buffer circuit depending on change of the power voltage VDD is shown to be large.
If the output signal OUT having unstable current driving ability of is used as base current of a NPN-bipolar transistor, the change amount of collector current which is output current of the amplified NPN-bipolar transistor becomes larger.
Furthermore, the semiconductor memory device using the large change amount of output current has unstable power and causes mis-operations.